As semiconductor devices and circuits are scaled down to sub-0.25 xcexcm for VLSI technology, the gate oxide is thinner than about 50 xc3x85 and its quality becomes more and more important. However, it has been found that the polysilicon/silicon gate is etched and penetrated after HF solution etch processes. This attacks the gate oxide film and results in gate oxide failure making is difficult to maintain device control and the device easily breaks down or becomes leaky. Thus, in order to improve device performance and reliability, gate oxide integrity improvement becomes very important.
U.S. Pat. No. 6,207,492 to Tzeng et al. describes a salicide process and a rapid process oxidation (RPO) process in forming logic devices with salicide shapes on gate structures and on heavily doped source/drain regions with simultaneously forming embedded DRAM devices with salicide shapes only on gate structures.
U.S. Pat. No. 6,218,311 to McKee et al. describes a post-etch treatment of an etch-damaged semiconductor device that includes forming a protective cover over an oxidizable section of the semiconductor device.
U.S. Pat. No. 5,998,292 to Black et al. describes a method for interconnecting, through high-density micro-post wiring, multiple semiconductor wafers with lengths of about a millimeter or below.
U.S. Pat. No. 6,194,296 to Lien describes polycide structures and method for making the same.
Accordingly, it is an object of an embodiment of the present invention to provide an improved cleaning process to improve device gate oxide integrity.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a substrate having a gate oxide layer formed is provided. A gate layer is formed over the gate oxide layer. An RPO layer is formed over the gate layer. A patterned photoresist layer is formed over the RPO layer exposing a portion of the RPO layer. The portion of the RPO layer having a patterned photoresist residue thereover. The structure is subjected to a dry plasma or gas treatment to clean the exposed portion of the RPO layer and removing the patterned photoresist residue. The RFO layer is etched using the patterned photoresist layer as a mask to expose a portion of the gate layer. The dry plasma or gas treatment preventing formation of defects or voids in the RPO layer and the poly gate layer during etching of the RPO layer. A metal layer is formed over at least the exposed portion of the gate layer. The structure is annealed to convert at least a portion of the metal layer and at least a portion of the underlying portion of the gate layer to form a gate silicide portion.